The present invention relates to a semiconductor memory device which is provided with a floating gate and a control gate and can rewrite data.
FIG. 1 schematically illustrates a configuration which is one example of a memory cell used in a conventional erasable-programmable read only memory (EPROM). This memory cell is of the n-channel type and includes a p-type substrate 1 of monocrystalline silicon; n.sup.+ -type source and drain regions 2 and 3; a floating gate 4 formed on a channel region between the source and drain regions 2 and 3, through a gate insulating layer 5; a control gate 6; and source and drain electrodes 7 and 8.
In executing the data write operation of the memory device shown in FIG. 1, a high level voltage, e.g., a voltage not lower than +20 V, is applied to the control gate 6 and drain electrode 8. Thus, impact ionization or the avalanche phenomenon is caused near the drain region 3, due to the electrons flowing from the source region 2 toward the drain region 3, thereby causing a number of electron-hole pairs to be generated. Part of the electrons among these electron-hole pairs are implanted in the floating gate 4, through the gate insulating layer 5, and are trapped therein. In this way, when the electrons are trapped in the floating gate 4, the memory cell has a high threshold voltage; so that, even if the readout voltage is applied to the control gate 6, this memory cell will not be turned ON. In a case where the electrons are not trapped in the floating gate 4, the memory cell has a low threshold voltage, so that this memory cell will be turned ON in response to the readout voltage applied to the control gate 6.
The data which was once written can be erased by radiating ultraviolet rays toward the memory cell.
Recently, the development in the micro processing technology of semiconductor devices has been advanced and, in particular, the shortening of the channel length has been promoted to improve the switching speed. This trend has been fairly pronounced in the field of EPROMs, where the channel length of each memory cell has been increasingly shortened. However, this shortening of the channel length has a negative influence on the characteristics of the semiconductor device. For example, the electric field formed in the channel region due to the voltage applied between the source and drain regions becomes strong, in conjunction with the shortening of the channel length. Therefore, even in the case where a relatively low voltage, e.g. a voltage of about +5 V is applied to the drain region and control gate in the readout operation of the EPROM, the electrons flowing from the source region to the drain region are accelerated to a sufficiently high speed, so that they may have a high enough level of kinetic energy to cause impact ionization in the channel region near the drain region. Therefore, in the EPROM which is highly integrated and is composed of memory cells, each of which has a shortened channel length, the electrons are injected into and trapped in the floating gate of the memory cell having a low threshold voltage in the readout operation, causing the threshold voltage of this memory cell to be raised. Such an erroneous write operation can be prevented, by reducing the power source voltage. However, the reduction of this power voltage results in a reduction in the speed of data readout from the memory cell.